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ASAHI KASEI
[AK9813B]
AK9813B
12ch 8bit D/A Converter with EEPROM
General Description
The AK9813B includes 12 channel, 8bit D/A converters with on-chip output buffer amps and it is capable to store the input digital data of each DAC by on-chip non-volatile CMOS EEPROM. The AK9813B is optimally designed for various circuit adjustments for consumer and industrial equipments and it is ideally suited for replacing mechanical trimmers.
Features
EEPROM SECTION 12 words x 8bit x 4 organization for DAC D/A CONVERTER SECTION 12 channels Resolution : 8bit DNL : -1 to +2 LSB INL : 1.5 LSB Analog Output Voltage Range : GND to VCC Operating Voltage Range Digital section : 2.7V to 5.5V Analog section : 4.5V to 5.5V, 2.7V to 3.6V 24pin VSOP
CLK DI
VDD VSS
-+
DO SEL ECL CS/LD EA0 EA1
Shift Register Control Logic Channel & Address Decoder
8bit Latch 8bit Latch
8
8bit D/A 8bit D/A
AO1
8
-+
AO2
8
VCC GND
384bit (12 x 8bit x 4)
EEPROM
8bit Latch 8bit Latch
8
8bit D/A 8bit D/A
-+
AO11
8
-+
AO12
Block Diagram
DAD04E-01 -1-
2002/11
ASAHI KASEI
[AK9813B]
Ordering Guide Model AK9813BF Pin Layout Temp. Range -40 to +85C Package 24-pin VSOP
AK9813BF
AO1 AO2 AO3 AO4 AO5 AO6 AO7 AO8 AO9 AO10 AO11 AO12 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VSS GND EA1 EA0 DI CLK CS/LD DO ECL SEL VCC VDD
24pin VSOP
DAD04E-01 -2-
2002/11
ASAHI KASEI
[AK9813B]
Pin Description (1) No. 20 Pin Name DI I/O I Function Serial Data Input Pin SEL=High : 16bit data input format SEL=Low : 14bit data input format (SEL=High: CS I/F) AK9813B reads out the data with LSB first in the 16bit shift register to DO pin synchronously with falling edge of CLK. When the CS pin is high level, the DO pin becomes high impedance. In STATUS mode, the DO pin outputs Ready/Busy status. (SEL=Low: LD I/F) AK9813B reads out the data with MSB first in the 14bit shift register to DO pin synchronously with falling edge of CLK. In WRITE mode, the DO pin outputs Ready/Busy status. 19 CLK I Shift Clock Input Pin (Schmitt-trigger input) AK9813B takes in the data from DI pin synchronously with rising edge of the CLK pin. The data are transferred to the internal shift register. Chip Select Input Pin (Schmitt-trigger input) The CS/LD is internally pulled up to VCC. (SEL=High: CS I/F) After the CS pin changes from high level to low level while the CLK pin is high level, the AK9813B can input the data to the internal shift register and takes in the data from the DI pin synchronously with the rising edge of the CLK pin. After the CS pin changes from high level to low level while the CLK pin is low level, the AK9813B becomes the status mode and reads out the Ready/Busy status to the DO pin. When the CS pin changes from low level to high level regardless of Low/High level of the CLK pin, the AK9813B removes from the status mode to the normal mode. The CS pin usually should be kept at high level. (SEL=Low: LD I/F) When the LD pin receives high pulse, the data of the internal shift register is transferred to the internal decoder or the register for D/A. The LD pin usually should be kept at low level.
17
DO
O
18
CS/LD
I
DAD04E-01 -3-
2002/11
ASAHI KASEI
[AK9813B]
Pin Description (2) No. 1 12 14 23 13 24 21 22 Pin Name AO1 AO12 VCC GND VDD VSS EA0 EA1 I/O O Function 8bit D/A outputs with OP-AMP I Digital section Power Supply Pin Digital section Ground Pin OP-AMP and D/A section Power Supply OP-AMP and D/A section Ground (SEL=High: CS I/F) In AUTO READ operation and ECL operation, the address of EEPROM is selected by the EA0 and the EA1 pins. (SEL=Low: LD I/F) The address of EEPROM is selected by the EA0 and the EA1 pins. 16 ECL I When the ECL pin receives high pulse, the data in EEPROM is automatically loaded to each corresponding D/A, starting from AO1 to AO12 in order. Then each D/A output is settled to pre-determined value. Input Data Format Select Pin SEL=High : CS I/F SEL=Low : LD I/F After power-up, this pin should be kept either at "high" or "Low."
15
SEL
I
DAD04E-01 -4-
2002/11
ASAHI KASEI
[AK9813B]
Data Configuration
AK9813B have a shift register in order to control the chip. When the SEL pin is "H"(CS I/F), the shift register becomes 16bit configuration and the data on the DI pin should be loaded with LSB first. When the SEL pin is "L"(LD I/F), the shift register becomes 14bit configuration and the data on the DI pin is loaded with MSB first. The following description shows the configuration of the shift register. The data set consist of 2-bits for the control of the internal EEPROM, 2-bits for the address of the EEPROM (CS I/F only), 4-bits for select of D/A converter and 8-bits for the digital input data of the 8bit D/A converter and total data set is 16bits or 14bits.
Shift register configuration: SEL=High (CS I/F) MSB Last
A1 A0 CL WR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
LSB First
D0
EEPROM ADDRESS
EEPROM CONTROL
SELECTION FOR D/A CONVERTER
DIGITAL INPUT DATA FOR D/A CONVERTER
OUTPUT VOLTAGE FOR D/A CONVERTER
D7 0 0 0 1 1 D6 0 0 0 1 1 D5 0 0 0 1 1 D4 0 0 0 1 1 D3 0 0 0 1 1 D2 0 0 0 1 1 D1 0 0 1 1 1 D0 0 1 0 0 1 OUTPUT VOLTAGE FOR D/A GND=VSS VDD/255 x 1 VDD/255 x 2 VDD/255 x 254 VDD A1 0 0 1 1 A0 0 1 0 1 EEPROM ADDRESS ADDRESS: 0 ADDRESS: 1 ADDRESS: 2 ADDRESS: 3
D/A CONVERTER CHANNEL SELECTION
D11 0 0 0 0 0 0 0 0 D10 0 0 0 0 1 1 1 1 D9 0 0 1 1 0 0 1 1 D8 0 1 0 1 0 1 0 1 D/A CHANNEL Don't Care AO1 AO2 AO3 AO4 AO5 AO6 AO7 D11 1 1 1 1 1 1 1 1 D10 0 0 0 0 1 1 1 1 D9 0 0 1 1 0 0 1 1 D8 0 1 0 1 0 1 0 1 D/A CHANNEL AO8 AO9 AO10 AO11 AO12 Can't use Can't use Don't Care
(NOTE) Above "Don't Care" state is valid only when AK9813B is in DAC mode or WRITE mode. Refer to the following section "Instruction Set" about mode.
DAD04E-01 -5-
2002/11
ASAHI KASEI
[AK9813B]
Shift register configuration: SEL=Low (LD I/F) LSB Last
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 WR
MSB First
CL
DIGITAL INPUT DATA FOR D/A CONVERTER
SELECTION FOR D/A CONVERTER
EEPROM CONTROL
OUTPUT VOLTAGE FOR D/A CONVERTER
D0 0 1 0 0 1 D1 0 0 1 1 1 D2 0 0 0 1 1 D3 0 0 0 1 1 D4 0 0 0 1 1 D5 0 0 0 1 1 D6 0 0 0 1 1 D7 0 0 0 1 1 OUTPUT VOLTAGE FOR D/A GND=VSS VDD/255 x 1 VDD/255 x 2 VDD/255 x 254 VDD EA1 0 0 1 1 EA0 0 1 0 1 EEPROM ADDRESS ADDRESS: 0 ADDRESS: 1 ADDRESS: 2 ADDRESS: 3
NOTE) EEPROM ADDRESS is selected by the EA0 and EA1 pins.
D/A CONVERTER CHANNEL SELECTION
D8 0 0 0 0 0 0 0 0 D9 0 0 0 0 1 1 1 1 D10 0 0 1 1 0 0 1 1 D11 0 1 0 1 0 1 0 1 D/A CHANNEL Don't Care AO1 AO2 AO3 AO4 AO5 AO6 AO7 D8 1 1 1 1 1 1 1 1 D9 0 0 0 0 1 1 1 1 D10 0 0 1 1 0 0 1 1 D11 0 1 0 1 0 1 0 1 D/A CHANNEL AO8 AO9 AO10 AO11 AO12 Can't use Can't use Don't Care
(NOTE) Above "Don't Care" state is valid only when AK9813B is in DAC mode or WRITE mode. Refer to the following section "Instruction Set" about mode.
DAD04E-01 -6-
2002/11
ASAHI KASEI
[AK9813B]
Instruction Set
The AK9813B can be controlled for the following mode. The following mode is common to the LD I/F and the CS IF. When LD I/F is selected, "A1" and "A0" are set by the external pins (EA0 pin and EA1 pin). DAC mode (External DI pin -> D/A converter) X Don't Care
A1 X A0 X CL WR D11 D10 D9 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function D/A output D/A CHANNEL Digital Data for D/A
CALL mode (Internal EEPROM -> D/A converter)
A1 A0 CL WR D11 D10 D9 1 0 D8 D7 X D6 X D5 X D4 X D3 X D2 X D1 X D0 X READ
ADDRESS
X Don't Care
Function
D/A CHANNEL
The output of D/A converter is set by the data in the internal EEPROM. ALL CALL mode (Internal EEPROM -> D/A converter)
A1 A0 CL WR D11 D10 D9 1 0 0 0 0 D8 0 D7 X D6 X D5 X D4 X D3 X D2 X D1 X D0 X
ADDRESS
X Don't Care
Function ALL CHANNEL READ
The outputs of all D/A converters are set by the data in the internal EEPROM. ...Internal ECL function WRITE ENABLE mode (Internal EEPROM WRITE ENABLE)
A1 X A0 X CL WR D11 D10 D9 1 1 0 0 0 D8 0 D7 X D6 X D5 X D4 X D3 X D2 X D1 X D0 X
X Don't Care
Function WRITE ENABLE
After WRITE ENABLE mode is executed, the programming to the internal EEPROM is enabled. Upon power-up and after the execution of the ECL function, the AK9813B is in the programming disable state. WRITE DISABLE mode (Internal EEPROM WRITE DISABLE)
A1 X A0 X CL WR D11 D10 D9 1 1 1 1 1 D8 1 D7 X D6 X D5 X D4 X D3 X D2 X D1 X D0 X
X Don't Care
Function WRITE DISABLE
After WRITE DISABLE mode is executed, the programming to the internal EEPROM is disabled. WRITE mode (External DI pin -> Internal EEPROM)
A1 A0 CL WR D11 D10 D9 0 1 D8 D7 D6 D5 D4 D3 D2 D1 D0 WRITE
ADDRESS
X Don't Care
Function
D/A CHANNEL
Digital Data for D/A
The digital data for D/A (D0 to D7) is written into the specified address in the internal EEPROM. The state of the internal EEPROM must be the programming enable state. READ mode (Internal EEPROM -> External DO pin)
A1 A0 CL WR D11 D10 D9 1 1 D8 D7 X D6 X D5 X D4 X D3 X D2 X D1 X D0 X
ADDRESS
X Don't Care
Function EEPROM DATA output
D/A CHANNEL
The DO pin outputs the data in the internal EEPROM synchronously with the falling edge of the input pulse of the CLK pin.
DAD04E-01 -7-
2002/11
ASAHI KASEI
[AK9813B]
Functional Description
Timing Diagram for CS I/F (SEL="H") 1. DAC mode: The internal EEPROM is not used.
DI CLK CS/LD DO AO1 - 12 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 WR CL A0 A1
2. WRITE ENABLE/DISABLE mode: The programming state of the internal EEPROM is set.
"1111"=WRITE DISABLE
DI CLK CS/LD DO
D8
D9
D10 D11
WR
CL
A0
A1
"0000"=WRITE ENABLE
3. CALL mode: The output of the D/A is set by the data in the internal EEPROM.
DI CLK CS/LD DO AO1 - 12 Output of selected channel changes. D8 D9 D10 D11 WR CL A0 A1
DAD04E-01 -8-
2002/11
ASAHI KASEI
[AK9813B]
4. ALL CALL mode: The outputs of the all D/As are set by the data in the internal EEPROM.
DI CLK CS/LD DO AO1 - 12 D8 D9 D10 D11 WR CL A0 A1
*The D/A outputs are set from AO1 to AO12 in order.
5. WRITE mode: The digital input data for D/A converter is written into the internal EEPROM.
DI CLK CS/LD DO AO1 - 12 No change D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 WR CL A0 A1
6. READ mode: The data in the internal EEPROM is read from the DO pin.
DI CLK CS/LD DO AO1 - 12 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 WR CL A0 A1 Data for next mode or all "0"
No change
DAD04E-01 -9-
2002/11
ASAHI KASEI
[AK9813B]
7. STATUS mode: The DO pin outputs the Ready/Busy status from the DO pin.
CLK CS/LD DO AO1 - 12 Ready/Busy No change
* : When the Ready/Busy is "L", it indicates the busy status. When AK9813B executes the CALL, ALL CALL, READ, AUTOREAD or ECL operation, the DO pin outputs "L".
8. ECL function: For "H" pulse to the ECL pin, the data in the selected address in the internal EEPROM is automatically loaded. Then each D/A converter output is settled to pre-determined value.
EA0, EA1 ECL AO1 - 12 INVALID
*Analog output is set from AO1 to AO12 in order.
EEPROM ADDRESS
9. Transfer mode for the cascade connection In case that AK9813B devices are connected in cascade, the AK9813B under programming cycle can transfer the data to the other AK9813B. The some AK9813B devices can be operated by the common CS signal at the same time. Please note that the input data into to the AK9813B under programming cycle should be all "0" when the CS pin is changed from "L" to "H". If data except all "0" is input into the AK9813B under programming cycle, accidental data disturbance may occur.
DI CLK
Data to the next DAC
CL
A0
A1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9 D10 D11 WR
CL
A0
A1
CS/LD DO AO1 - 12 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 WR CL A0 A1
Output data to the next DAC
No operation
DAD04E-01 - 10 -
2002/11
ASAHI KASEI
[AK9813B]
Timing Diagram for LD I/F (SEL ="L") 1. DAC mode: The internal EEPROM is not used.
DI CLK CS/LD DO AO1 - 12 CL WR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
2. WRITE ENABLE/DISABLE mode: The programming state of internal EEPROM is set.
"1111"=WRITE DISABLE
DI CLK CS/LD
CL
WR
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
"0000"=WRITE ENABLE
3. CALL mode: The output of the D/A is set by the data in the internal EEPROM.
DI CLK EA0, EA1 CS/LD DO AO1 - 12 CL WR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DAD04E-01 - 11 -
2002/11
ASAHI KASEI
[AK9813B]
4. ALL CALL mode: The outputs of the all D/As are set by the data in the internal EEPROM.
DI CLK EA0, EA1 CS/LD DO AO1 - 12 CL WR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
*The D/A outputs are set from AO1 to AO12 in order.
5. WRITE mode: The digital input data for D/A converter is written into the internal EEPROM.
DI CLK EA0, EA1 CS/LD DO AO1 - 12 CL WR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
READY/BUSY Output
No change
(NOTE) * In case that AK9813B devices are connected in cascade, when a AK9813B device is under programming cycle, the AK9813B device under programming cycle can not transfer the data to the other AK9813B device and some AK9813B devices can not be operated by the common CS signal at the same time. * While programming cycle, the CS/LD pin should be "L". * When the Ready/Busy signal from the DO pin is verified, the CS pin should be changed from "H" to "L" and kept at "L". If the CS pin is kept at "H", the Ready/Busy signal does not output correctly.
DAD04E-01 - 12 -
2002/11
ASAHI KASEI
[AK9813B]
6. READ mode: The data in the internal EEPROM is read from the DO pin.
DI CLK EA0, EA1 CS/LD DO CL WR D11 D10 D9 D8 D7 * * D1 ** ** ** ** D0
1
**
7
Data for next mode or all "0"
8 9 10 11 12 13 14
** ** ** **
INVALID DATA (6bit)
D7
D6
D5
D4
D3
D2
D1
D0
VALID DATA (8bit: MSB first)
AO1 - 12
**
**
Not change
7. ECL function: When the ECL pin received high pulse, the data in EEPROM is automatically loaded to each corresponding D/A, and starting from AO1 to AO12 in order. Then each D/A output is settled to pre-determined value.
EA0, EA1 ECL AO1 - 12 INVALID
* Analog outputs are set from AO1 to AO12 in order.
EEPROM ADDRESS
DAD04E-01 - 13 -
2002/11
ASAHI KASEI
[AK9813B]
Absolute Maximum Ratings
Parameter Power Supply Input Voltage Ambient Temperature Storage Temperature Symbol VCC VIO Ta Tst Spec. -0.6 to +7.0 -0.6 to VCC+0.6 -40 to +85 -65 to +150 Unit V V C C
Recommended Operating Conditions
Parameter Power Supply 1 (Digital section) Power Supply 2 (DAC, AMP sections) Analog Output Source Current 1 Analog Output Sink Current 1 Analog Output Source Current 2 Analog Output Sink Current 2 Analog Output Load Capacitance Symbol VCC VDD1 VDD2 IAL VDD=4.5V to 5.5V IAH IAL VDD=2.7V to 3.6V IAH AOC 500 1.0 A F 1 500 mA A Conditions Min 2.7 4.5 2.7 Typ Max 5.5 5.5 3.6 1 Units V V V mA
DAD04E-01 - 14 -
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ASAHI KASEI
[AK9813B]
Electrical Characteristics
DC Characteristics (1) Digital Section (VCC=2.7V to 5.5V, VDD=4.5V to 5.5V or 2.7V to 3.6V, GND, VSS=0V, Ta=-40C to +85C) Parameter Symbol Pin Power Supply VCC (Digital Section) Operating Current ICC VCC (READ) (1) (2) Leakage Current ILI CLK, DI CS/LD EA0, EA1 ECL, SEL DI EA0, EA1 ECL, SEL CS/LD CLK Conditions Min 2.7 Max 5.5 1.1 -1.0 1.0 Units V mA A
CLK=1MHz VIN=VCC
High Level Input Voltage 1 Low Level Input Voltage 1 High Level Input Voltage 2 Low Level Input Voltage 2 High Level Output Voltage
VIH VIL VIH VIL VOH1 VOH2 VOL1 VOL2
0.5xVCC 0.2xVCC 0.6xVCC 0.15xVCC
V V V V V V 0.4 0.4 V V
DO
Low Level Output Voltage
4.5VVCC5.5V IOH=-400A 2.7VVCC<4.5V IOH=-200A 4.5VVCC5.5V IOH=1.0mA 2.7VVCC<4.5V IOH=1.0mA
VCC-0.4 0.7xVCC
(1) All input pins are connected to either VCC or GND. (2) DO=OPEN
DAD04E-01 - 15 -
2002/11
ASAHI KASEI
[AK9813B]
(2) Analog Section (2-1) VDD=4.5V to 5.5V (VCC=2.7V to 5.5V, VDD=4.5V to 5.5V, GND, VSS=0V, Ta=-40C to +85C) Parameter Power Supply 1 (Analog Section) Power Dissipation 1 (Analog Section) Resolution Integral (3) Non-Linearity: INL Differential Non-Linearity: DNL Buffer-AMP Minimum Output Voltage 1 Buffer-AMP Minimum Output Voltage 2 Buffer-AMP Minimum Output Voltage 3 Buffer-AMP Minimum Output Voltage 4 Buffer-AMP Minimum Output Voltage 5 Buffer-AMP Maximum Output Voltage 1 Buffer-AMP Maximum Output Voltage 2 Buffer-AMP Maximum Output Voltage 3 Buffer-AMP Maximum Output Voltage 4 Buffer-AMP Maximum Output Voltage 5 Symbol VDD1 IDD1 Res LE DLE VAOL1 VAOL2 VAOL3 VAOL4 VAOL5 VAOH1 VAOH2 VAOH3 VAOH4 VAOH5 AO1 AO12 AO1 AO12 Pin VDD AOx=OPEN 8 AOx=OPEN 0.05VAO VDD-0.1V IAL=0A Data=00(Hex) IAL=500A Data=00(Hex) IAH=500A Data=00(Hex) IAL=1mA Data=00(Hex) IAH=1mA Data=00(Hex) IAH=0A Data=FF(Hex) IAL=500A Data=FF(Hex) IAH=500A Data=FF(Hex) IAL=1mA Data=FF(Hex) IAH=1mA Data=FF(Hex) -1.5 -1.0 GND -0.1 GND -0.2 GND VDD-0.1 VDD-0.2 VDD-0.2 VDD-0.3 VDD-0.3 1.5 2.0 0.05 0.1 0.1 0.2 0.2 VDD VDD VDD+0.2 VDD VDD+0.3 7.0 mA bits LSB LSB V V V V V V V V V V Conditions Min 4.5 Typ 5.0 Max 5.5 Units V
(3) Integral Non-Linearity is the error between the actual line and the ideal line. The ideal line exhibits a perfect linear D/A converter output characteristic between the input digital data"00" and the input digital data"FF".
DAD04E-01 - 16 -
2002/11
ASAHI KASEI
[AK9813B]
(2-2) VDD=2.7V to 3.6V (VCC=2.7V to 3.6V, VDD=2.7V to 3.6V, GND, VSS=0V, Ta=-40C to +85C) Parameter Power Supply 2 (Analog Section) Power Dissipation 2 (Analog Section) Resolution Integral (4) Non-Linearity: INL Differential Non-Linearity: DNL Output Voltage for Input Data "05" Output Voltage for Input Data "FA" Buffer-AMP Minimum Output Voltage 6 Buffer-AMP Minimum Output Voltage 7 Buffer-AMP Minimum Output Voltage 8 Buffer-AMP Minimum Output Voltage 9 Buffer-AMP Minimum Output Voltage 10 Buffer-AMP Maximum Output Voltage 6 Buffer-AMP Maximum Output Voltage 7 Buffer-AMP Maximum Output Voltage 8 Buffer-AMP Maximum Output Voltage 9 Buffer-AMP Maximum Output Voltage 10 VAOL6 VAOL7 VAOL8 VAOL9 VAOL10 VAOH6 VAOH7 VAOH8 VAOH9 VAOH10 AO1 AO12 Symbol VDD2 IDD2 Res LE DLE AO1 AO12 Pin VDD AOx=OPEN 8 AOx=OPEN 0.15VAO VDD-0.15V AOx=OPEN VDD=3.3V IAL=0A Data=00(Hex) IAL=250A Data=00(Hex) IAH=250A Data=00(Hex) IAL=500A Data=00(Hex) IAH=500A Data=00(Hex) IAH=0A Data=FF(Hex) IAL=250A Data=FF(Hex) IAH=250A Data=FF(Hex) IAL=500A Data=FF(Hex) IAH=500A Data=FF(Hex) -1.5 -1.0 0.1 3.15 GND -0.1 GND -0.2 GND VDD-0.1 VDD-0.2 VDD-0.2 VDD-0.3 VDD-0.3 3.25 0.05 0.1 0.1 0.2 0.2 VDD VDD VDD+0.2 VDD VDD+0.3 1.5 2.0 0.15 4.0 mA bits LSB LSB V V V V V V V V V V V V Conditions Min 2.7 Typ Max 3.6 Units V
(4) Integral Non-Linearity is the error between the actual line and the ideal line. The ideal line exhibits a perfect linear D/A converter output characteristic between the input digital data"05" and the input digital data"FA".
DAD04E-01 - 17 -
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ASAHI KASEI
[AK9813B]
AC Characteristics (1) CS I/F, LD I/F: Common Timing (VCC=2.7V to 5.5V, VDD=4.5V to 5.5V or 2.7V to 3.6V, GND, VSS=0V, Ta=-40C to +85C) Parameter VCC Rise Time Auto Address Hold Time Auto Read Time ECL "H" Pulse Width External Call Time Address Set Up Time ECL Address Hold Time Repeat Call Prohibition Time *1: 4.5VVCC5.5V *2: 2.7VVCC<4.5V
(AC test measurement done at 90% and 10%points of VCC.) VCC 10% 90% tVCR tVAH EA0 / EA1 tPOR D/A Output(AO12) INVALID (EA0/EA1 should be set at the same timing as VCC.)
Symbol tVCR tVAH tPOR tECW1 tECW2 tECL tESU1 tESU2 tEAH tECC1 tESCC2
Conditions
Min 3.5
Max 50 3.5
Test Load 2 *1 *2 Test Load 2 *1 *2 *1 *2
100 250 3.5 50 100 3.5 20 100
Units ms ms ms ns ns ms ns ns ms ns ns

ECL
tECW tESU tEAH
tECC
EA0 / EA1 tECL D/A Output (AO12) INVALID
DAD04E-01 - 18 -
2002/11
ASAHI KASEI
[AK9813B]
(2) CS I/F Timing (VCC=2.7V to 5.5V, VDD=4.5V to 5.5V or 2.7V to 3.6V, GND, VSS=0V, Ta=-40C to +85C) Parameter Clock "L" Pulse Width Clock "H" Pulse Width Clock Rising Time Clock Falling Time Data Set Up Time Data Hold Time CS Set Up Time CS Hold Time CS "H" Hold Time Symbol tCKL1 tCKL2 tCKH1 tCKH2 tCr tCf tDSU1 tDSU2 tDHD1 tDHD2 tCSU1 tCSU2 tCCH tCSH Conditions *5 *6 *5 *6 Min 200 500 200 500 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms s ms ns ns ns ns ns ns s s ms ns ns ns
200 *5 *6 *5 *6 *5 *6 DAC etc. WRITE CALL, READ ALL CALL *3, *4, *5 *3, *4, *6 *4 30 150 60 150 100 150 200 100 250 7 15 3.5 200 500 200 500 170 300 200 250 3.5 100 100 250
Data Output Enable Time Data Output Float Delay Data Output Delay D/A Output Setting Time
tDOD1 tDOD2 tDOZ1 tDOZ2 tDOC1 tDOC2 tCSD
Test Load 1 DAC CALL ALL CALL
*5 *6 *5 *6 *5 *6 Test Load 2 Test Load 2 Test Load 2 *5 *6
Status Set Up Time Status Hold Time
tSSU tSHD1 tSHD2
*3: Please refer to "DAC etc" regarding CS "H" Hold Time before status mode execute. *4: If READY/BUSY="H" is confirmed in status mode in the WRITE mode, the CS pin can be changed to "L" shorter than the values specified on above. Please refer to "DAC etc" regarding CS "H" Hold Time in case that AK9813B to be connected in cascade is under programming cycle (READY/BUSY="L"). *5: 4.5VVCC5.5V *6: 2.7VVCC<4.5V
DAD04E-01 - 19 -
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ASAHI KASEI
[AK9813B]

tCr CLK tCKL DI tCSU CS/LD tCSD D/A Output tDOD tDOC DO tDOC tDOZ 90% 10% tDSU tDHD tCCH tCSH tCKH tCf

CLK tSSU CS/LD tDOD DO (READY/BUSY STATUS) tDOZ tSHD
DAD04E-01 - 20 -
2002/11
ASAHI KASEI
[AK9813B]
(3) LD I/F Timing (VCC=2.7V to 5.5V, VDD=4.5V to 5.5V or 2.7V to 3.6V, GND, VSS=0V, Ta=-40C to +85C) Parameter Clock "L" Pulse Width Clock "H" Pulse Width Clock Rising Time Clock Falling Time Data Set Up Time Data Hold Time Load Set Up Time Load Hold Time Load "H" Pulse Width Symbol tCKL1 tCKL2 tCKH1 tCKH2 tCr tCf tDCH1 tDCH2 tCHD1 tCHD2 tCHL tLDC1 tLDC2 tLDH1 tLDH2 tLDH3 tDO1 tDO2 tLDD Conditions *5 *6 *5 *6 Min 200 500 200 500 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns ns s s ms ns ns ns ns ms s ns ns s ms s ms
200 *5 *6 *5 *6 *5 *6 *5 *6 30 150 60 150 200 100 250 100 250 5 170 300 200 250 3.5 100 200 20 100 7 0.8 20 100 15 3.5 15 3.5
Data Output Delay D/A Output Setting Time
Address Set Up Time Write Address Hold Time Programming Cycle Ready Signal Delay Repeat Write Prohibition Time Read Hold Time Read Address Hold Time
tASU1 tASU2 tWAHD1 tWAHD2 tWRT tRYD tRYH1 tRYH2 tRHD tRAHD
modes except READ mode READ mode Test Load 1 *5 Test Load 1 *6 DAC Test Load 2 CALL Test Load 2 ALL CALL Test Load 2 *5 *6 *5 *6 *7 Test Load 1 Test Load 1 *5 Test Load 2 *6 CALL, READ mode ALL CALL mode CALL, READ mode ALL CALL mode
*7: If READY/BUSY="L" is confirmed in status mode in the WRITE mode, the next operation can be started.
DAD04E-01 - 21 -
2002/11
ASAHI KASEI
[AK9813B]

tCr CLK tCKL DI tDCH CS/LD tCHL D/A Output tDO DO tDO tLDD 90% 10% tCHD tLDH tCKH tCf tLDC

CLK
CS/LD tASU EA0 / EA1 tWRT DO tRYD READY/BUSY STATUS tRYH tWAHD
* Please refer to the data timing regarding the input timing for the DI pin.
DAD04E-01 - 22 -
2002/11
ASAHI KASEI
[AK9813B]

CLK tRHD CS/LD tASU EA0 / EA1 tLDD D/A Output tRAHD
* Please refer to the data timing regarding the input timing for the DI pin.
AC measurement circuit Test Load 1
Test Point
Test Load 2
Test Point
CL=20pF ~100pF
RAL= 10K
CL=50pF
AC test point Digital Input / Output Level : 50% / 20% of VCC Analog Output Level : 90% / 10% of VCC
DAD04E-01 - 23 -
2002/11
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.

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